31412 sy/22912 sy 20110916 s00002 no.a2011-1/8 http://onsemi.com semiconductor components industries, llc, 2013 june, 2013 LA4425PV overview the LA4425PV is a 5w power amplifier with very few external parts. encapsulated in a surface mount package [ssop44k (275 mil)], it is designed for operation without a heat sink. only two external parts (only in/out coupling capacitors). almost no evaluation, adjustment and check of its functions as a power ic required, enabling control to be simplified and set patterns to be further miniaturized. functions ? wide operation supply range 5 to 16v ? on-chip protection: - over-voltage protection - thermal protection - output d.c. short protection . ? on-chip pop noise reducing circuit specifications maximum ratings at ta = 25 c parameter symbol conditions ratings unit maximum supply voltage v cc max rg = 0 18 v surge maximum supply voltage v cc surge giant pulse 200ms rise time 1ms 50 v maximum output current i o peak 3.3 a allowable power dissipation pd max when mounted on the specified pcb 5.15 w operating temperature topr -40 to +85 c storage temperature tstg -40 to +150 c orderin g numbe r : ena2011a orderin g numbe r : ena2011a monolithic linear ic 5w power amplifier with very few external parts for car radio and car stereo stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above the recommended oper ating conditions is not implied. extended exposure to stresses above the recommended operating conditions may affect device reliabili ty.
LA4425PV no.a2011-2/8 operating conditions at ta = 25 c, parameter symbol conditions ratings unit recommended supply voltage v cc 13.2 v recommended load resistance r l 4 operating voltage range v cc op 5 to 16 v operating load resistance range r l op under conditions where maximum ratings are not exceeded 2 to 8 electrical characteristics at ta = 25 c, v cc = 13.2v, r l = 4 , f = 1 khz, rg = 600 , specified board/specified circuit parameter symbol conditions ratings unit min typ max quiescent current i cco 65 130 ma voltage gain v g v o = 0dbm 43 45 47 db output power p o 1 13.2 v / 4 , thd = 10% 4 5 w p o 2 14.4 v / 4 , thd = 10% 5 6 w total harmonic distortion thd v o = 2vrms 0.1 1.0 % output noise voltage v no rg = 0 , bpf = 20 hz to 20 khz 0.15 0.5 mv ripple rejection ratio svrr1 rg = 0 , bpf = 20 hz to 20 khz v r = 0dbm, f r = 100hz 30 40 db svrr2 rg = 0 , bpf = 20 hz to 20 khz v r = 0dbm, f r = 1khz 47 db over-voltage attack v cc x rg = 0 21.5 v starting time t s 0.35 s input resistance r in 50 k roll-off frequency f l 40 hz f h 90 khz package dimensions unit : mm (typ) 3333 sanyo : ssop44k(275mil) 15.0 7.6 (3.5) (4.7) 5.6 0.5 0.22 0.2 0.65 (0.68) 0.1 (1.5) 1.7max top view side view side view bottom view 122 23 44
LA4425PV no.a2011-3/8 board specifications of the pdmax - ta measurement (LA4425PV specified pcb) size: 70mm 70mm 1.6mm 3 (four layer boards) copper foil thickness: l1/l4=18m, l2/l3=35m materials: fr-4 (glass cloth matrix epoxy resin) l1: figure of copper wiring pattern l2: figure of copper wiring pattern l3: figure of copper wiring pattern l4: figure of copper wiring pattern notes: the data for the case with the exposed die-pad substrate mo unted shows the values when 95% or more of the exposed die-pad is wet. 1. for the set design, employ the derating design with sufficient margin. 2. stresses to be derated include the voltage, current, junctio n temperature, power loss, a nd mechanical stresses such as vibration, impact, and tension. accordingly, the design must ensure these st resses to be as low or small as possible. the guideline for ordinary derating is shown below: (1) maximum value 80% or less for the voltage ratings (2) maximum value 80% or less for the current ratings (3) maximum value 80% or le ss for the temperature ratings 3. after the set has been designed, be sure to verify the design with the actual product. confirm the solder joint state and verify also the reliability of solder joint for the exposed die-pad, etc. any void or deterioration, if observed in the solder joint of these parts, causes deteriorated therma l conduction, possibly resulting in thermal destruction of ic. -40 -20 0 20 40 60 80 100 0 6.0 1.0 2.0 3.0 4.0 5.0 pd max -- ta 5.15 2.68 ambient temperature, ta -- c maximum power dissipation, pd max -- w
LA4425PV no.a2011-4/8 pin assignment ? connect exposed die pad on the back side to gnd with a large pattern. ? pins whose names are not given next to the pin numbers are all ?nc pins? that are not connected to the chip inside the package, and they must not be used as relay pins. application circuit example ? on-chip overvoltage protection ? on-chip thermal protection ? on-chip pop noise reducing circuit ? on-chip output d.c. short protection pin voltage at v cc = 13.2v characteristics input pre gnd power gnd output v cc pin no. 10 14, 15 30, 31 33, 34 36, 37 pin voltage (reference value) ( 2v be ) 1.4v 0v 0v ( 1/2v cc ) 6.5v (v cc ) 13.2v + + + 10 14 30 34 36 v cc LA4425PV in pregnd powergnd 15 31 33 37 out out 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 lv4425pv 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 out v cc v cc powergnd pregnd in pregnd powergnd
LA4425PV ps no.a2011-5/8 ic usage notes ? maximum ratings if the ic is used in the vicinity of the maximum ratings, even a slight variation in conditions may cause the maximum ratings to be exceeded, there by leading to a breakdown. ? printed circuit board when drawing the printed circuit pattern, refer to the sample printed circuit pattern. be careful not to form a feedback loop between input and output. always use both pins of the pre gnd, power gnd, out and v cc when designing the layout. ? exposed die-pad the exposed die pad on the back side of the ic must be connected to gnd with a large pattern surface area. ? load resistance and misoperation it should be noted that when r l < 2 and v cc is high, and the switch is turned ?on? when setting is for a signal (thd = 10%), the ground detector (current voltage schmitt circuit) operates momentarily. ? starting time (t s ) this is set at 0.35sec/typ, but it can be made shorter by maki ng input capacitor ci smaller, or longer by making it larger. ? pop noise the pop noise prevention circuit operates to reduce pop until rg reaches 50k . however, if rg is left open, the charging route of input capacitor ci is lost, so the pop noise reduction circuit stops operating and click noises become louder. ? vg/osc the voltage gain is fixed at 45db inside the ic. it is impossible to change it externally. phase compensation capacitors (350pf/total) are connected between individual stages inside the ic, and the open loop gain is low. in addition, the upper and lower drives are made equivalent so that final stage current gain is adjusted, providing a measure against unwanted high-frequency parasitic oscillation peculiar to power ic?s. ? btl connection connection is impossible with ic alone.
LA4425PV ps no.a2011-6/8 p o -- v in 23 23 57 100 57 10 1.0 10 7 5 1.0 7 5 0.1 7 5 3 2 3 2 3 2 7 5 0.1 23 57 1.0 23 57 10 10 7 5 3 2 1.0 7 5 0.1 7 5 3 2 thd -- p o 1 0 -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 10 23 5 100 23 5 1k 23 5 10k 23 5 100k f response thd -- f 7 5 3 2 1.0 7 5 3 2 0.1 3 357 100 23 57 1k 23 57 10k 23 f h f l 100 80 60 40 20 0 024681012141618202224 12 10 8 6 4 2 0 0 2 4 6 8 10 12 14 16 18 20 22 24 i cco -- v cc v n -- v cc supply voltage, v cc -- v supply voltage, v cc -- v quiescent current, i cco -- ma output pin voltage, v n -- v input voltage, v in -- mv output power, p o -- w output power, p o -- w total harmonic distortion, thd -- % total harmonic distortion, thd -- % response -- db frequency, f -- hz frequency, f -- hz thd -- v cc 5 3 2 1.0 7 5 3 2 0.1 7 5 6 8 10 12 14 16 18 20 p o -- v cc 12 10 8 6 4 2 0 8 101214161820 supply voltage, v cc -- v total harmonic distortion, thd -- % supply voltage, v cc -- v output power, p o -- w
LA4425PV ps no.a2011-7/8 i cc , pd -- p o 700 600 500 400 300 200 100 0 7 6 5 4 3 2 1 0 7 0.1 23 57 1.0 23 57 10 i cc , pd -- p o 0 200 0 2 4 6 8 10 400 600 800 1000 1200 7 0.1 23 57 1.0 23 57 10 2 svrr -- v r v no -- rg svrr -- f r svrr -- v cc 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 7 1k 23 57 10k 23 57 100k 2 50 40 30 20 10 0 8 9 10 11 12 13 14 15 16 17 18 19 50 40 30 20 10 0 0 200 400 600 800 1000 1200 50 40 30 20 10 0 057 100 23 57 1k 2 output power, p o -- w output power, p o -- w current drain, i cc -- ma current drain, i cc -- ma power dissipation, pd -- w power dissipation, pd -- w i cc v cc =16v v cc =13.2v i cc v cc =16v v cc =13.2v supply voltage, v cc -- v output noise voltage, v no -- mv ripple rejection ratio, svrr -- db ripple rejection ratio, svrr -- db ripple rejection ratio, svrr -- db power supply ripple, v r -- mvrms ripple frequency, f r -- hz t s 0.2s/div gnd 2v/div 0.2s/div gnd 2v/div
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